Senior Design Lead

EducationDegree: Bachelor's or Master's degree in Electronics & Communication Engineering (ECE), Electrical Engineering (EE), VLSI Design, or a closely related fieldLanguages: Proficiency in Verilog, SystemVerilog, and core concepts of UVM.Digital Logic: Strong foundational knowledge in digital logic design, finite state machines (FSM), FIFO architectures, and clocking concepts.EDA Tools: Familiarity with industry-standard simulation and debugging tools (e.g., Synopsys VCS, Siemens QuestaSim, Cadence Xcelium/Verdi).Protocols: Deep, authoritative knowledge of high-speed protocols (e.g., SPI, I2C,PCIe, NVMe, Ethernet, USB) or complex bus architectures (e.g., AMBA AXI/CHI/ACE)."Job Summaryandidates with 5 to 7 years experience is mandatory Good understanding of ASIC/SoC life cycle Has participated in multiple ASIC/SoC verification till tapeout stage Full chip TB Architecture definition Experience writing ASIC/SoC testplans UVM based testbench development 1.Experience in ASIC/SoC Testbench
definition 2.Experience to Build and maintain reusable block-level and sub-system testbenches using SystemVerilog and the Universal Verification Methodology (UVM)." SV functional coverage, Assertions coding 1.Expertise & hands-on experience in OVM/UVM methodologies using SV 2.Experience to Write, execute, and debug constrained-random and directed test cases based on defined test plans. C based TB development 1. Experience in developing TB components for SOC with C, SV Test case development, coding, execution, bug analysis 1. Experience in developing TB components, including functional coverage implementation and assertion coding 2. Experience Set up functional coverage, write system assertions (SVA), and analyze code coverage metrics to identify untested gaps in the design logic. 3.Debug complex simulation failures using waveform viewer tools to isolate design bugs from testbench issues. 4. Experience in SOC C based tests coding & debugging Gate Level Simulation Experience in Gate level
simulation & netlist debugging Regressions, coverage analysis Experience in regression failure analysis Functional and Code Coverage closure participate in verification closure Experience in Perl/Shell scripting EducationDegree: Bachelor's or Master's degree in Electronics & Communication Engineering (ECE), Electrical Engineering (EE), VLSI Design, or a closely related field Core Technical Skills Languages: Proficiency in Verilog, SystemVerilog, and core concepts of UVM. Digital Logic: Strong foundational knowledge in digital logic design, finite state machines (FSM), FIFO architectures, and clocking concepts. EDA Tools: Familiarity with industry-standard simulation and debugging tools (e.g., Synopsys VCS, Siemens QuestaSim, Cadence Xcelium/Verdi). Protocols: Deep, authoritative knowledge of high-speed protocols (e.g., SPI, I2C,PCIe, NVMe, Ethernet, USB) or complex bus architectures (e.g., AMBA AXI/CHI/ACE)." Scripting: Basic comfort working in a Linux environment and using scripting
languages like Python, Tcl, or Perl for automation. Key Responsibilitiesandidates with 5 to 7 years experience is mandatory Good understanding of ASIC/SoC life cycle Has participated in multiple ASIC/SoC verification till tapeout stage Full chip TB Architecture definition Experience writing ASIC/SoC testplans UVM based testbench development 1.Experience in ASIC/SoC Testbench definition 2.Experience to Build and maintain reusable block-level and sub-system testbenches using SystemVerilog and the Universal Verification Methodology (UVM)." SV functional coverage, Assertions coding 1.Expertise & hands-on experience in OVM/UVM methodologies using SV 2.Experience to Write, execute, and debug constrained-random and directed test cases based on defined test plans. C based TB development 1. Experience in developing TB components for SOC with C, SV Test case development, coding, execution, bug analysis 1. Experience in developing TB components, including functional
coverage implementation and assertion coding 2. Experience Set up functional coverage, write system assertions (SVA), and analyze code coverage metrics to identify untested gaps in the design logic. 3.Debug complex simulation failures using waveform viewer tools to isolate design bugs from testbench issues. 4. Experience in SOC C based tests coding & debugging Gate Level Simulation Experience in Gate level simulation & netlist debugging Regressions, coverage analysis Experience in regression failure analysis Functional and Code Coverage closure participate in verification closure Experience in Perl/Shell scripting EducationDegree: Bachelor's or Master's degree in Electronics & Communication Engineering (ECE), Electrical Engineering (EE), VLSI Design, or a closely related field Core Technical Skills Languages: Proficiency in Verilog, SystemVerilog, and core concepts of UVM. Digital Logic: Strong foundational knowledge in digital logic design, finite state machines
(FSM), FIFO architectures, and clocking concepts. EDA Tools: Familiarity with industry-standard simulation and debugging tools (e.g., Synopsys VCS, Siemens QuestaSim, Cadence Xcelium/Verdi). Protocols: Deep, authoritative knowledge of high-speed protocols (e.g., SPI, I2C,PCIe, NVMe, Ethernet, USB) or complex bus architectures (e.g., AMBA AXI/CHI/ACE)." Scripting: Basic comfort working in a Linux environment and using scripting languages like Python, Tcl, or Perl for automation. Skill RequirementsOther Requirements