Research Software / Hardware Developer

University of Surrey

Research Software / Hardware Developer

£54395

University of Surrey, Guildford

  • Full time
  • Temporary
  • Onsite working

Posted 3 weeks ago, 23 May | Get your application in now before you miss out!

Closing date: Closing date not specified

job Ref: 90e4de431078499694825d0b8442da1f

Full Job Description

The successful candidates will be part of a group that focuses on research and development in the field of Open Radio Access Networks (Open RAN), with a specific emphasis on Advanced Physical (PHY) Layer designs, Radio Resource Management (RRM) for 5G-NR systems. The post holders will be expected to design, develop and validate efficient processing architectures in the context Open RAN based 5G-NR systems focusing on PHY layer and RRM, and targeting x86 general-purpose processors and/or Field-Programmable Gate Arrays (FPGAs) using RTL. Displaying a high degree of autonomy, the successful candidate will find novel solutions to complex problems, as defined by standardisation committees and the Wireless Systems Lab group. The post holder will be expected to be able to set, define and work towards achieving targets, disseminate results and document work done.
About ICS
ICS is the largest academic research institute in Europe specialising in all aspects of ICT (Information and Communication Technologies). It is home to over 200 researchers with expertise in all communication and broadcasting systems and has developed the best in class large scale testbeds for research and innovation and enjoys the state-of-the-art lab and computing facilities.
Established in 2012, 5GIC is the world's first dedicated centre in researching end-to-end aspects of 5G and works closely with national and international leading academic institutes and key industrial partners. In November 2020, 6GIC was officially launched with parallel research undertaken in both 5G+ and 6G for 2030+.

The post holder must have expertise in the following:
# Experience in design and development of algorithms targeting high throughput and low-latency on x86 general-purpose processors and/or Xilinx FPGAs using RTL.
# Recent experience in the development of PHY layer processing algorithms (e.g., forward error correction), and/or RRM algorithms (e.g. MAC scheduler).
# An overall working knowledge of 3GPP cellular networks (e.g.,: LTE, 5GNR).
# Good understanding of signal processing for wireless communication systems.
# Experience in development on Linux operating systems
# Good understanding of Open RAN related concepts
It would be desirable but not essential for the post holder to also have:
# Prior experience with wireless research platforms (e.g., Open Air Interface, srsRAN).
# Experience with a high-speed FPGA protocol, e.g., PCIe or 10GE.